An embodiment relates to a program method of a flash memory device and, more particularly, to a program method of a flash memory device, which is capable of reducing the irregularity of a threshold voltage resulting from the interference effect of a flash memory device having multi-level cells.
In recent years, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and do not require the refresh function of rewriting data at specific intervals. In order to develop large capacity memory devices capable of storing a large amount of data, research is being carried out on technologies for the high integration of memory devices. Accordingly, active research is being carried out on a flash memory.
A flash memory is mainly divided into a NAND flash memory and a NOR flash memory. The NOR flash memory has an excellent random access time characteristic because of its structure in which memory cells are respectively connected to bit lines and word lines. The NAND flash memory is excellent in terms of having high integration level because of its structure in which memory cells are connected in series, thereby requiring only one contact per cell string. Accordingly, the NAND structure is for the most part used in a high-integrated flash memory.
Recently, in order to further increase the integration of a flash memory, active research is being carried out on a multi-bit cell which is capable of storing plural data in one memory cell. This type of a memory cell is generally called a multi-level cell (MLC). A memory cell capable of storing a single bit is called a single level cell (SLC).
The MLC is generally configured to have two or more threshold voltage distributions and is capable of storing two or more data corresponding to the respective threshold voltage distributions. Accordingly, since one cell of the MLC can be divided into four or more levels as compared with the SLC having two levels, the bit number of the MLC can be two or more times the bit number of the SLC.
In order to embody this MLC, it is important to reduce a shift in the threshold voltage of a cell. One of the factors to change the threshold voltage of a cell is an interference effect resulting from capacitance between cells.
FIG. 1 is a diagram showing the distributions of a threshold voltage for illustrating a known program method of a flash memory device.
The memory cell array of a flash memory device generally has a string structure in which memory cells are respectively connected in series to even bit lines and odd bit lines. The even and odd bit lines adjoin to each other.
During the program operation of the flash memory device, a program voltage (for example, 15 V) is first applied to the word line of a first memory cell coupled to the even bit line, so the first memory cell is programmed with a threshold voltage distribution indicated by A.
Next, a program voltage (for example, 15 V) is applied to the word line of a second memory cell coupled to an odd bit line adjacent to the first memory cell, so the second memory cell is programmed with a threshold voltage distribution indicated by A′. In this case, the threshold voltage distribution of the first memory cell may move from A to B because of an interference effect during the program operation of the second memory cell.
The shift in the threshold voltage deteriorates the program characteristic of a flash memory device. In particular, in the case of a flash memory device having a multi-level cell, sensing margin may be reduced because of a shift in the threshold voltage.